Capacitor With 3D NAND Memory

ABSTRACT

An integrated circuit includes a 3D NAND memory array with a stack of conductive strips and a capacitor with a stack of capacitor terminal strips. Multiple conductive strips in the stack of conductive strips, and multiple capacitor terminal strips of the stack of capacitor terminal strips, share a same plurality of plane positions relative to the substrate. Different plane positions in the same plurality of plane positions characterize different capacitor terminal strips in the stack of capacitor terminal strips and different conductive strips in the stack of conductive strips, and a same plane position characterizing both a conductive strip in the stack of conductive strips and a capacitor terminal strip in the stack of capacitor terminal strips indicates that the conductive strip and the capacitor terminal strip have a same vertical position relative to each other.

CROSS-REFERENCE TO OTHER APPLICATIONS

This application is related to the following co-pending U.S. patentapplications: U.S. patent application Ser. No. 13/049,303, filed 16 Mar.2011, entitled REDUCED NUMBER OF MASK FOR IC DEVICE WITH STACKED CONTACTLEVELS, now U.S. Pat. No. 8,598,032; and U.S. patent application Ser.No. 13/114,931, filed 24 May 2011, entitled MULTILAYER CONNECTIONSTRUCTURE AND MAKING METHOD, now U.S. Patent No. 8,383,512.

BACKGROUND OF THE INVENTION

Capacitors are electronic devices including two terminals separated byinsulating material. When there is a voltage difference between the twoterminals, an electric field is created between the two terminalsthereby storing electrical energy. The amount of electrical charge thatcan be stored on a capacitor per volt across the terminals is referredto as capacitance. Terminals are typically in the form of plates ofvarious shapes, surface contours and sizes. The capacitance is generallya function of the dielectric constant κ of the dielectric layer,directly proportional to the area of the opposed terminals and inverselyproportional to the distance between the terminals. Placing two or morecapacitors in parallel results in a total capacitance of the combinationthat is equal to the sum of the capacitances of the individualcapacitors. Placing two or more capacitors in series results in a totalcapacitance of the combination that is less than the capacitance of anyof the individual capacitors. Series connected capacitors are commonlyused in high-voltage situations because the high-voltage is dividedamong the capacitors. While providing capacitors of various sizes isusually not a problem outside of an integrated circuit, conventionalintegrated circuits are limited to relatively small capacitors becauseof size limitations. See, for example, U.S. Pat. No. 5,497,016.

A stack of capacitors connected in parallel has a low area footprintfrom the bottom capacitor in the stack of capacitors, and yet a largecapacitance from the summed capacitance of the capacitors in the stackconnected in parallel. However, the stacked capacitor is fabricated bymany steps which results in increased complexity and cost of the overallintegrated circuit. It would be desirable to take advantage of the lowarea footprint, large capacitance of the stacked capacitor, whileminimizing additional fabrication complexity and cost resulting from theaddition of the stacked capacitor to an integrated circuit.

BRIEF SUMMARY OF THE INVENTION

Various aspects of the technology involve integrated circuits havingboth a 3D NAND memory array with a stack of conductive strips, and astacked capacitor with a stack of capacitor terminal strips. Because theintegrated circuit is already being fabricated to include a 3D NANDarray, overall complexity is changed little from fabricating stacks ofconductive strips for a capacitor in addition to the NAND memory array.

One aspect of the technology includes an integrated circuit with asubstrate, a 3D NAND memory array with a stack of conductive strips, anda stacked capacitor with a stack of capacitor terminal strips. Multipleconductive strips in the stack of conductive strips, and multiplecapacitor terminal strips of the stack of capacitor terminal strips,share a same plurality of vertical distances from the substrate.

In some embodiments of the technology, the stack of conductive strips isat least one of: transistor channels in the 3D NAND memory array,conductors routing signals that select memory cells in the 3D NANDmemory array, and conductors routing output from the 3D NAND memoryarray. In one embodiment of the technology, the 3D NAND memory array isa vertical gate memory array, and the conductive strips in the stack areNAND transistor channels in the vertical gate memory array. In oneembodiment of the technology, the 3D NAND memory array is a verticalchannel memory array, and the conductive strips in the stack are wordlines in the vertical channel memory array.

In one embodiment of the technology, the stack of capacitor terminalstrips includes a first plurality of capacitor terminal stripsalternating with a second plurality of capacitor terminal strips. Thefirst plurality of capacitor terminal strips are electrically connectedtogether and the second plurality of capacitor terminal strips areelectrically connected together.

In one embodiment of the technology, the stack of capacitor terminalstrips has a first end and a second end. Multiple capacitor terminalstrips in the stack of capacitor terminal strips are electricallyconnected together at the first end, and multiple capacitor terminalstrips in the stack of capacitor terminal strips are electricallyconnected together at the second end. The embodiment further comprises aconductive plug electrically connected to at least one of the capacitorterminal strips at an intermediate point in between the first end andthe second end.

In one embodiment of the technology, the stack of capacitor terminalstrips is one of a plurality of stacks of capacitor terminal stripshaving lengths between first ends and second ends. The plurality ofstacks of capacitor terminal strips include the first plurality ofcapacitor terminal strips alternating with the second plurality ofcapacitor terminal strips. The first plurality of capacitor terminalstrips in the plurality of stacks of capacitor terminal strips areelectrically coupled together via the first ends and at intermediatepoints in between the first ends and second ends.

Another aspect of the technology is a computer readable mediumcomprising a layout for an integrated circuit including designs for aplurality of masks. The integrated circuit includes a 3D NAND memoryarray with a stack of conductive strips as described herein, and acapacitor with a stack of capacitor terminal strips as described herein.Multiple masks in the plurality of masks each define at least oneconductive strip in the stack of conductive strips and at least onecapacitor terminal strip in the stack of capacitor terminal strips.

A further aspect of the technology is a method of making an integratedcircuit comprises:

-   -   making a 3D NAND memory array with a stack of conductive strips        as described herein, and a stacked capacitor with a stack of        capacitor terminal strips as described herein, including:        -   in a same etch, defining the stack of conductive strips and            the stack of capacitor terminal strips.

Other features, aspects and advantages of the present invention can beseen on review the figures, the detailed description, and the claimswhich follow.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is an end view of stacks of conductive material for both acapacitor and a 3D NAND array on a same substrate.

FIG. 2 is a side view of a capacitor with a stack of conductive materialfrom FIG. 1.

FIGS. 3 and 4 are circuit diagrams of different ways to interconnectindividual capacitors in a stack of conductive material, resulting indifferent overall capacitances of the stack of conductive material as awhole.

FIG. 5 is a perspective illustration of a three-dimensional, verticalgate NAND-flash memory device with stacks of conductive material fromFIG. 1.

FIG. 6 is a perspective illustration of an alternativethree-dimensional, vertical channel NAND-flash memory device with stacksof conductive material from FIG. 1.

FIGS. 7-8 are steps in a process for forming the stacks of conductivematerial for both a capacitor and a 3D NAND array on a same substratefrom FIG. 1.

FIG. 9 is a top view of a capacitor with stacks of conductive material,with an overlay of mask regions defining varying etch depths forelectrical conductors.

FIG. 10 is a side view of a capacitor with stacks of conductivematerial.

FIGS. 11-14 illustrate a sequence of steps creating electricalconductors at an interconnect region in contact with extensions of theterminal layers, such as shown in the example of FIG. 10, providingelectrical access to a serpentine, stacked plate capacitor assembly.

FIG. 15 is a simplified block diagram of an integrated circuit withstacks of conductive material for both a capacitor and a 3D NAND arrayon a same substrate.

FIG. 16 is a simplified block diagram of a computer system thatimplements software incorporating aspects of the present technology.

FIG. 16A shows a nontransitory computer readable medium storing computerreadable data with aspects of the present technology.

DETAILED DESCRIPTION OF THE INVENTION

The following description will typically be with reference to specificstructural embodiments and methods. It is to be understood that there isno intention to limit the invention to the specifically disclosedembodiments and methods but that the invention may be practiced usingother features, elements, methods and embodiments. Preferred embodimentsare described to illustrate the present invention, not to limit itsscope, which is defined by the claims. Those of ordinary skill in theart will recognize a variety of equivalent variations on the descriptionthat follows. Like elements in various embodiments are commonly referredto with like reference numerals.

It is widely recognized that capacitance is very useful electroniccircuitry, but is expensive and has manufacturing difficulties whenmanufactured in semiconductors. Capacitance can be used to help reducevoltage variations and can be used to help save data in memory, such asSRAM, DRAM and Flash, either during normal operations or due tounexpected power failures. While there are system-level products forproviding such capacitance, there may be advantages to providing it atthe semiconductor level, including system cost, power and reliability.

FIG. 1 is an end view of stacks of conductive material for both acapacitor and a 3D NAND array on a same substrate. In this end view, thestrips of conductive material and strips of insulator extend into andout of the page to the extent of the lengths of the strips of conductivematerial and strips of insulator.

The same insulator layer 10 is the base for stacks of conductivematerial that are in both a capacitor and a 3D NAND array. Insulatorlayer 10 is over a substrate layer 9. Stacks 15 a and 15 b are includedin capacitor devices. Stacks 15 c and 15 d are included in a 3D NANDarray.

The zigzag lines through the insulator layer 10 indicate that thecapacitor and a 3D NAND array are spaced apart on the same insulatorlayer 10. In another embodiment, the stacks are spaced apart on a sameconductive substrate, and the bottom of each stack is an insulatorstrip.

In stacks 15 a, 15 b, 15 c, and 15 d, strips of conductive materialalternate with strips of insulator. For example, in stack 15 a, aninsulator strip 12 a electrically insulates proximate strips ofconductive material 11 a and 13 a in the same stack from each other.Insulator strip 14 a is above top-most conductive material strip 13 a. Asame arrangement of insulator strips and conductive material strips isin stacks 15 b, 15 c, and 15 d.

Conductive material strips 13 a, 13 b, 13 c, and 13 d share a same planeposition and thus have a same vertical position relative to each other.Conductive material strips 11 a, 11 b, 11 c, and 11 d also share a sameplane position and thus have a same vertical position relative to eachother. Conductive material strips 13 a, 13 b, 13 c, and 13 d have adifferent plane position relative to conductive material strips 11 a, 11b, 11 c, and 11 d; thus conductive material strips 13 a, 13 b, 13 c, and13 d have a different vertical position relative to conductive materialstrips 11 a, 11 b, 11 c, and 11 d.

In an embodiment where the stacks share a common conductive substrate,the bottom insulator strip on the common conductive substrate isolatesthe conductive substrate shared by multiple stacks from the bottom-mostconductive strip in each stack.

The strips of conductive material in both the capacitor terminal stacksand the 3D NAND array can be implemented using polysilicon or epitaxialsingle crystal silicon having n-type or p-type doping. The insulatorstrips can be implemented for example using silicon dioxide, othersilicon oxides, or silicon nitride.

The 3D NAND array of the integrated circuit includes stacks 15 c and 15d of strips of conductive material. So complexity and cost of theintegrated circuit is not appreciably increased from the furtherinclusion of stacks 15 a and 15 b of strips of conductive material ascapacitors of the integrated circuit.

FIG. 2 is a side view of a capacitor with a stack of conductive materialfrom FIG. 1. In this side view, the strips of conductive material andstrips of insulator extend into and out of the page to the extent of thewidths of the strips of conductive material and strips of insulator.

Insulator layer 10 is the base for the stack of conductive material thatin a capacitor device. Insulator layer 10 is over a substrate layer 9.Additional stacks of conductive material for additional capacitor devicecan be elsewhere on the insulator layer 10. Also, a 3D NAND array withmultiple stacks of conductive material is elsewhere on the insulatorlayer 10. In another embodiment, the stack is on a conductive substrate,and the bottom of each stack is an insulator strip. The capacitorsuppresses parasitic capacitance by omitting the well-to-substratecapacitance of well capacitors, which could be in the range of abouttenths of picofarads.

In the stack, strips of conductive material alternate with strips ofinsulator. The stack includes capacitor terminal strip 1 21, capacitorterminal strip 2 23, capacitor terminal strip 3 25, capacitor terminalstrip 4 27, capacitor terminal strip 5 29, capacitor terminal strip 631, capacitor terminal strip 7 33, and capacitor terminal strip 8 35.The stack also includes insulator strip 1 22, insulator strip 2 24,insulator strip 3 26, insulator strip 4 28, insulator strip 5 30,insulator strip 6 32, insulator strip 7 34, and insulator strip 8 36.Accordingly, the capacitor terminal strips alternate with insulatorstrips. An insulator strip electrically insulates proximate stripscapacitor terminal strips in the same stack from each other.

The strips of conductive material in both the capacitor terminal stacksand the 3D NAND array can be implemented using polysilicon or epitaxialsingle crystal silicon having n-type or p-type doping. The insulatorstrips can be implemented for example using silicon dioxide, othersilicon oxides, or silicon nitride.

Terminal connection circuit 1 37 and terminal connection circuit 2 38electrically connect together capacitor terminal strips. Such terminalconnection circuits electrically connect the multiple capacitors withinthe stack in parallel. As discussed below, the parallel connection sumsthe capacitances of the multiple capacitors within the stack, resultingin a high total capacitance of the stack. Terminal connection circuit 137 electrically connects the “odd” capacitor terminal strips, includingcapacitor terminal strip 1 21, capacitor terminal strip 3 25, capacitorterminal strip 5 29, and capacitor terminal strip 7 33. Terminalconnection circuit 2 38 electrically connects the “even” capacitorterminal strips, including capacitor terminal strip 2 23, capacitorterminal strip 4 27, capacitor terminal strip 6 31, and capacitorterminal strip 8 35. The stack includes seven capacitors each having arespective one of the insulator strips as the capacitor's intermediatedielectric. The seven capacitors each have two terminals, including afirst capacitor terminal which is one of the “odd” capacitor terminalstrips, and a second capacitor terminal which is one of the “even”capacitor terminal strips.

Other embodiments have more or fewer capacitors in the stack. Otherembodiments connect in parallel only a subset of the capacitors in thestack. Other embodiments connect in series two or more of the capacitorsin the stack. Other embodiments connect in series two or more of thecapacitors in the stack, and connect in parallel two or more of thecapacitors in the stack. Other embodiments allow one or more of theintermediate terminals to float, to allow more leeway in the layout.

FIGS. 3 and 4 are circuit diagrams of different ways to interconnectindividual capacitors in a stack of conductive material, resulting indifferent overall capacitances of the stack of conductive material as awhole.

The example of FIG. 3 has four capacitors connected to electricalconductors 46.0 and 46.1, 46.2 and 46.3, 46.4 and 46.5, and 46.6 and46.7. To make one large-capacitance capacitor, the individualcapacitors, identified as C₀₁, C₂₃, C₄₅ and C₆₇ in FIG. 3, can be placedin parallel. To do so, electrical conductors 46.0, 46.2, 46.4 and 46.6are shorted to one another as a first terminal 47 and electricalconductors 46.1, 46.3, 46.5 and 46.7 are shorted to one another as asecond terminal 48. Another example, shown in FIG. 4, shows each ofcapacitors C₀₁, C₂₃, C₄₅ and C₆₇ connected in series. While the totalcapacitance C_(T) for the FIG. 4 example is less than the capacitance ofany of the individual capacitors, placing the capacitors in series isuseful when working with high voltages because each capacitor only seesa fraction of the total voltage. Other embodiments can connectseries-connected capacitors and parallel-connected capacitors.

FIG. 5 is a perspective illustration of a three-dimensional, verticalgate NAND-flash memory device with stacks of conductive material fromFIG. 1. The device illustrated in FIG. 1 includes stacks of active linesin active layers of the array, alternating with insulating lines.Insulating material is removed from the drawing to expose additionalstructure. For example, insulating lines are removed between thesemiconductor lines in the stacks, and between the stacks ofsemiconductor lines.

In the example shown in FIG. 1, a multilayer array is formed on aninsulating layer, and includes a plurality of word lines 125-1, . . . ,125-N conformal with the plurality of stacks. The plurality of stacksincludes semiconductor lines 112, 113, 114, and 115 in multiple planes.Semiconductor lines in the same plane are electrically coupled togetherby bit line contact pads (e.g. 102B). The plurality of stacks are formedon a same substrate as stacks in capacitors, as shown in FIG. 1.

Bit line contact pads 112A, 113A, 114A, and 115A are on the near end ofthe figure terminate semiconductor lines, such as semiconductor lines112, 113, 114, and 115. As illustrated, these bit line contact pads112A, 113A, 114A, and 115A are electrically connected by interlayerconnectors to different bit lines in an overlying patterned metal layer,e.g. ML3, for connection to decoding circuitry to select planes withinthe array. These bit line contact pads 112A, 113A, 114A, and 115A can beformed over stepped substrate structures as discussed below, andpatterned at the same time that the plurality of stacks is defined.

Bit line contact pads 102B, 103B, 104B, and 105B on the far end of thefigure terminate semiconductor lines, such as semiconductor lines 102,103, 104, and 105. As illustrated, these bit line contact pads 102B,103B, 104B, and 105B are electrically connected by interlayer connectorsto different bit lines in an overlying patterned metal layer, e.g. ML3,for connection to decoding circuitry to select planes within the array.These bit line contact pads 102B, 103B, 104B, and 105B can be formedover stepped substrate structures as discussed below, and patterned atthe same time that the plurality of stacks is defined.

In this example, any given stack of semiconductor lines is coupled toeither the bit line contact pads 112A, 113A, 114A, and 115A, or the bitline contact pads 102B, 103B, 104B, and 105B, but not both. A stack ofsemiconductor bit lines has one of the two opposite orientations of bitline end-to-source line end orientation, or source line end-to-bit lineend orientation. For example, the stack of semiconductor lines 112, 113,114, and 115 has bit line end-to-source line end orientation; and thestack of semiconductor lines 102, 103, 104, and 105 has source lineend-to-bit line end orientation.

The stack of semiconductor lines 112, 113, 114, and 115 terminated bythe bit line contact pads 112A, 113A, 114A, and 115A, passes through SSLgate structure 119, ground select line GSL 126, word lines 125-1 WLthrough 125-N WL, ground select line GSL 127, and is terminated at theother end by source line 128. The stack of semiconductor lines 112, 113,114, and 115 does not reach the bit line structures 102B, 103B, 104B,and 105B.

The stack of semiconductor lines 102, 103, 104, and 105 terminated bythe bit line contact pads 102B, 103B, 104B, and 105B, passes through SSLgate structure 109, ground select line GSL 127, word lines 125-N WLthrough 125-1 WL, ground select line GSL 126, and is terminated at theother end by a source line (obscured by other parts of the figure). Thestack of semiconductor lines 102, 103, 104, and 105 does not reach thebit line structures 112A, 113A, 114A, and 115A.

A layer of memory material is disposed in interface regions atcross-points between surfaces of the semiconductor lines 112-115 and102-105 and the plurality of word lines 125-1 through 125-n. Groundselect lines GSL 126 and GSL 127 are conformal with the plurality ofstacks, similar to the word lines.

Every stack of semiconductor lines is terminated at one end by bit linecontact pads and at the other end by a source line. For example, thestack of semiconductor lines 112, 113, 114, and 115 is terminated by bitline contact pads 112A, 113A, 114A, and 115A, and terminated on theother end by a source line 128.

Bit lines and string select lines are formed at the metal layers ML1,ML2, and ML3. Bit lines are coupled to a plane decoder (not shown) inthe peripheral area on the circuit. String select lines are coupled to astring select line decoder (not shown) in the peripheral area on thecircuit.

The ground select lines GSL 126 and 127 can be patterned during the samestep that the word lines 125-1 through 125-n are defined. Ground selectdevices are formed at cross-points between surfaces of the plurality ofstacks and ground select lines GSL 126 and 127. The SSL gate structures119 and 109 can be patterned during the same step that the word lines125-1 through 125-n are defined. String select devices are formed atcross-points between surfaces of the plurality of stacks and stringselect (SSL) gate structures 119 and 109. These devices are coupled todecoding circuitry for selecting the strings within particular stacks inthe array.

FIG. 6 is a perspective illustration of an alternativethree-dimensional, vertical channel NAND-flash memory device with stacksof conductive material from FIG. 1.

The memory device includes an array of NAND strings of memory cells, andcan be a double-gate vertical channel memory array (DGVC). The memorydevice includes an integrated circuit substrate 201, and a plurality ofstacks of conductive strips alternating with insulating material. Thestacks include at least a bottom plane of conductive strips (GSL), aplurality of intermediate planes of conductive strips (WLs), and a topplane of conductive strips (SSLs). The stacks are formed on a samesubstrate as stacks in capacitors, as shown in FIG. 1.

For example, a stack 210 includes a bottom plane of conductive strips(GSL), a plurality of intermediate planes of conductive strips (WLs)ranging from WL₀ to WL_(N-1), and a top plane of conductive strips(SSLs), where N can be 8, 16, 32, 64 and so on. The insulating materialis removed from the drawing to expose additional structure. For example,the insulating material is removed between the conductive strips in thestacks, and is removed between the stacks of conductive strips.

In the example shown in FIG. 6, a plurality of bit line structures isarranged orthogonally over, having surfaces conformal with, theplurality of stacks, including inter-stack semiconductor body elements220 between the stacks and linking elements 230 over the stacksconnecting the semiconductor body elements 220.

The memory device includes memory elements in interface regions atcross-points 280 between side surfaces of the conductive strips in theplurality of intermediate planes (WLs) in the stacks and the inter-stacksemiconductor body elements 220 of the plurality of bit line structures.

A reference conductor 260 is disposed between the bottom plane (GSL) ofconductive strips and the integrated circuit substrate 201. At least onereference line structure is arranged orthogonally over the plurality ofstacks, including inter-stack semiconductor elements 240 between thestacks in electrical communication with the reference conductor 260, andlinking elements 250 over the stacks 210 connecting the inter-stacksemiconductor elements 240. The semiconductor elements 240 can have ahigher conductivity than the semiconductor body elements 220.

The memory device includes string select switches 290 at interfaceregions with the top plane of conductive strips, and reference selectswitches 270 at interface regions with the bottom plane (GSL) ofconductive strips.

In the example shown in FIG. 6, the memory device can further includedecoding circuitry coupled to the conductive strips in the plurality ofstacks. The decoding circuitry can include word line decoding circuits,and string selection line decoding circuits coupled to the top plane ofconductive strips (SSLs) in the plurality of stacks. String selectionlines in the top plane of conductive strips are independently coupled toand controlled by the string selection line decoding circuits.

Conductive strips in the intermediate planes (WLs), and conductivestrips in the bottom plane (GSL) are connected together to reducedecoder areas and consequently an overall size of the memory device.Conductive strips in the top plane (SSL) are individually decoded toallow correct bit line decoding.

The memory device can include contact pads which provide linkingelements, such as contact pads 261 and 262, connecting sets of wordlines in the intermediate planes (WL), and interlayer connectors, suchas interlayer connectors 271 and 272, coupled to landing areas in thecontact pads 261 and 262, and to the word line decoding circuits (notshown). The landing areas are at interface regions between bottomsurfaces of the interlayer connectors and top surfaces of the contactpads.

In the example shown in FIG. 6, interlayer connectors (e.g. 271 and 272)for sets of word lines at multiple layers in the plurality ofintermediate planes are arranged in a staircase structure, and areconnected to landing areas at two different layers in the plurality ofintermediate planes. The contact pads can be formed over a steppedsubstrate structure as described below.

The staircase structure can be formed in a vertical contact region nearthe boundary of a memory cell region for the array of memory cells and aperipheral region for components of peripheral circuits. The verticalcontact region can include contact pads 261 and 262, and interlayerconnectors 271 and 272.

The memory device can include ground selection line decoding circuitscoupled to the at least one bottom plane (GSL) of conductive strips inthe plurality of stacks. The memory device can include contact pads,such as a contact pad 263, connecting sets of ground selection lines inthe bottom plane (GSL) of conductive strips, and interlayer connectors,such as an interlayer connector 273, coupled to landing areas in thecontact pads, and to the ground selection line decoding circuits (notshown).

In the example shown in FIG. 6, the memory device includes a firstoverlying conductive layer (not shown) connected to the plurality of bitline structures, including a plurality of global bit lines coupled tosensing circuits. The memory device also includes a second overlyingconductive layer (not shown) connected to the at least one referenceconductor structure, coupled to a reference voltage source.

Insulating layers in the stack can be the same as or different from theother layers. Representative insulating materials that can be usedinclude a silicon oxide, a silicon nitride, a silicon oxynitride,silicate, or other materials. Low dielectric constant (low-k) materialshaving a dielectric constant smaller than that of silicon dioxide, suchas SiCHO_(x), can be used. High dielectric constant (high-k) materialshaving a dielectric constant greater than that of silicon dioxide, suchas HfO_(x), HfON, AlO_(x), RuO_(x), TiO_(x), can be used also.

Conductor or semiconductor layers in the stack can be the same as ordifferent from the other layers. Representative materials that can beused include semiconductors including undoped and doped polysilicon(using dopants such as As, P, B), combinations of semiconductorstructures, silicides including TiSi, CoSi, oxide semiconductors,including InZnO, InGaZnO, and combinations of semiconductors andsilicides. Conductive layers in the stack can also be a metal, aconductive compound, or combinations of materials including Al, Cu, W,Ti, Co, Ni, TiN, TaN, TaA1N, and others.

FIGS. 7-8 are steps in a process for forming the stacks of conductivematerial for both a capacitor and a 3D NAND array on a same substratefrom FIG. 1.

In FIG. 7, a structure is shown which results from alternatingdeposition of insulating layers 210, 212, 214 and semiconductor layers211, 213 formed using doped semiconductors for example in a blanketdeposition in the array area of a chip. Depending on the implementation,the semiconductor layers 211, 213 can be implemented using polysiliconor epitaxial single crystal silicon having n-type or p-type doping. Atypical thickness range of the semiconductor layers is from 200 to 500angstroms.

Inter-level insulating layers 210, 212, 214 can be implemented forexample using silicon dioxide, other silicon oxides, or silicon nitride.These layers can be formed in a variety of ways, including low pressurechemical vapor deposition LPCVD processes available in the art. Thezigzag lines through the insulator layer 210 indicate that the capacitorand a 3D NAND array are spaced apart on the same insulator layer 210. Inanother embodiment, the stacks are spaced apart on a same conductivesubstrate, and the bottom of each stack is an insulator strip.

FIG. 8 shows the result of a first lithographic patterning step used todefine a plurality of ridge-shaped stacks 250 of semiconductor strips,where the semiconductor strips are implemented using the material of thesemiconductor layers 211, 213, and separated by the insulating layers212, 214. Deep, high aspect ratio trenches can be formed in the stack,supporting many layers, using lithography based processes applying acarbon hard mask and reactive ion etching.

The same insulator layer 210 is the base for stacks of conductivematerial that are in both a capacitor and a 3D NAND array. Stack 215 ais included in a capacitor device. Stack 15 b is included in a 3D NANDarray.

Conductive material strips 213 a and 213 b share a same plane positionand thus have a same vertical position relative to each other.Conductive material strips 211 a and 211 b also share a same planeposition and thus have a same vertical position relative to each other.Conductive material strips 213 a and 213 b have a different planeposition relative to conductive material strips 211 a and 211 b; thusconductive material strips 213 a and 213 b have a different verticalposition relative to conductive material strips 211 a and 211 b.

The zigzag lines through the insulator layer 210 indicate that thecapacitor and a 3D NAND array are spaced apart on the same insulatorlayer 210. In another embodiment, the stacks are spaced apart on a sameconductive substrate, and the bottom of each stack is an insulatorstrip.

The various methods typically use a series of deposition and etchingsteps to do so. Different methods are discussed in Xie, Peng and Smith,Bruce W., Analysis of Higher-Order Pitch Division for Sub-32 nmLithography, Optical Microlithography XXII, Proc. of SPIE Vol. 7274,72741Y, © 2009 SPIE. Multiple patterning methods are also described inU.S. patent application Ser. No. 12/981,121, filed 29 Dec. 2010,entitled MULTIPLE PATTERNING METHOD, having a common assignee and acommon inventor with this application.

Other dielectrics can be used, including low dielectric constant (low-k)materials such as silicon nitride or other low-k dielectrics. In someexamples, the capacitor structures can be made on what could be called arough surface conductor so that the upper portion of substrate 12 andridges 16 would be made of electrical conductors and thus act as anelectrically conductive terminal layer. In general, the conductors canbe a metal or combination of metals, include Al, Cu, W, Ti, Co, Ni. Theconductors can also be metal compounds, such as TiN/TaN/AlCu, orsemiconductor compounds, such as heavily doped Si (using dopants such asAs, P, B.); silicides including TiSi, CoSi. Also, typical dielectricmaterials include SiO₂, SiN, SiON. However, high dielectric constant(high-k) materials having a dielectric constant greater than that ofsilicon dioxide, such as HfO_(x), HfON, AlO_(x), RuO_(x), TiO_(x), aregenerally preferred. The dielectric materials may also be a multi-layer,such as silicon oxide/silicon nitride, silicon oxide (ONO), siliconoxide, high-k dielectric, silicon oxide (O/high-k/O), which providehigher k values and create less concern about capacitance leakage.

A suitable deposition technique for dielectric layer 22 would be, forexample, atomic layer deposition ALD, high density plasma chemical vapordeposition HDCVD, low density plasma chemical vapor deposition LPCVD,etc., depending on the chosen materials. The process of depositing theterminal layers 20 and dielectric layers 22 proceeds until a desirednumber of serpentine plate capacitors 18 are created. The size of trenchwidth 26 and the ratio between trench width 26 and ridge height 32typically limits the number of terminal and dielectric layers 20, 22.The size of trench width 26 is usually greater than ridge width 30.

FIG. 9 is a top view of a capacitor with stacks of conductive material,with an overlay of mask regions defining varying etch depths forelectrical conductors. In this top view, the stacks of conductive stripsextend into and out of the page to the extent of the heights of thestacks.

Shown are the stacks of conductive material 15 e, 15 f, 15 g, 15 h, 15i, 15 j, 15 k, and 15 l. Other embodiments have fewer or more stacks ofconductive material. The stacks have lengths with a first end and asecond end. The first ends are interconnected electrically by terminalconnection circuit 1 37 and the second ends are interconnectedelectrically by terminal connection circuit 2 38. Terminal connectioncircuit 1 37 interconnects “odd” numbered layers of capacitor terminalstrips. Terminal connection circuit 2 38 interconnects “even” numberedlayers of capacitor terminal strips. Such interconnection can be seen inFIG. 2.

The dimensions of the capacitor terminal strips can be sufficientlylarge such that even the minimal resistance of the conductive stripsresults in unacceptably long RC delay. An example RC delay calculationof the capacitor in FIG. 2 follows:

$\begin{matrix}{{RC} = {(R)*(C)}} \\{= {\left( {{{Rs}\left( {L/W} \right)}/\left( {\# \mspace{14mu} {layers}\mspace{14mu} {in}\mspace{14mu} {parallel}} \right)} \right)*}} \\{\left( {\left( {\varepsilon_{0}{\varepsilon_{r}/{thickness}}} \right)\left( {{width}\mspace{14mu} {length}} \right)\left( {\# \mspace{14mu} {capacitors}\mspace{14mu} {in}\mspace{14mu} {parallel}} \right)} \right)} \\{= {\left( {10^{5}{\left( {1.8/1.376} \right)/(4)}} \right)*}} \\{\left( {\left( {8.864\mspace{14mu} 10^{- 14}\mspace{14mu} {3.9/\left( {250\mspace{14mu} 10^{- 8}} \right)}} \right)\left( {1.8\mspace{14mu} 1.376\mspace{14mu} 10^{- 8}} \right)(7)} \right)} \\{= {0.8\mspace{14mu} {nanoseconds}}}\end{matrix}$

This example is different in other embodiments, as the variables inother embodiments can be changed: the material which changes Rs andε_(r), the dimensions of the material which changes thickness, thelayout which changes L and W of the resistance, the # layers inparallel, and the # of capacitors in parallel.

To decrease the resistance and thus shorten the RC delay, the capacitorterminal strips at different layers can be coupled to terminalconnection circuit 1 37 or terminal connection circuit 2 38 not just atends of the stacks, but also at an intermediate position between thefirst ends and the second ends. Such more frequent terminal connectionsare called strap connections. Strap connections reduce the resistance Lin the example RC delay calculation.

The strap connections are defined by the overlay of mask regionsdefining varying etch depths for the strap connections. Mask region 306defines an etch depth of 4 layers. Mask regions 302 define an etch depthof 2 layers. Mask regions 304 define an etch depth of 1 layer. Incombination, the etch depths vary from 0 layers to 7 layers, dependingon the combination of mask regions 302, 304, and 306 which overlie eachother above particular stacks of conductive material. The conductivematerial stacks have the following combined etch depths for the strapconnections. 15 e has a 7 layer etch depth, 15 f has a 6 layer etchdepth, 15 g has a 5 layer etch depth, 15 h has a 4 layer etch depth, 15i has a 3 layer etch depth, 15 j has a 2 layer etch depth, 15 k has a 1layer etch depth, and 15 l has a 0 layer etch depth.

FIG. 10 is a side view of a capacitor with stacks of conductivematerial. The different layers of conductive material are contacted byconductive plugs of different depths. Such an array of conductive plugscan be used as the strap contacts or as the terminal connection circuitsin FIG. 9.

The staircase plugs can have the same pitch as the stacks of conductivematerial.

FIGS. 11-14 illustrate a sequence of steps creating electricalconductors at an interconnect region in contact with extensions of theterminal layers, such as shown in the example of FIG. 10.

The different terminal layer extensions 40 are identified in the figuresas terminal layer extensions 40.0 through 40.7 with the top most being40.0. The locations for the electrical conductors 46 for contact withthe corresponding terminal layer extensions 40 are labeled 0 through 7in the figures. Similar numbering occurs with dielectric layerextensions 42. When an interconnect region 44 is located at the top ofone or more dielectric ridges 16 or at the bottom of one or moretrenches 15, then terminal conductors 46 will directly contact theterminal layers 20 with terminal layer extensions 40 being unnecessary.

A first photoresist mask 50, shown in FIG. 11, is created on dielectriclayer extension 42.0 at electrical conductor locations 0, 2, 4, 6 and onthe far side of location 7. The regions covered by photoresist masks aresometimes referred to as mask regions. The regions not covered by firstphotoresist mask 50, sometimes referred to as etch regions, are thenetched one level through dielectric layer extension 42.0 and terminallayer extension 40.0 to create the structure shown in FIG. 11. Next, asshown in FIG. 12, first photoresist mask 50 is removed and then a secondphotoresist mask 54 is formed on the resulting structure of FIG. 12 tocover electrical conductor locations 0, 1, 4, 5, and on the far side oflocation 7. The structure is then etched two levels at the exposedregions to create the structure shown in FIG. 12. Next, secondphotoresist mask 54 is removed and a third photoresist mask 58 is formedto cover electrical conductor locations 0, 1, 2, 3 and on the far sideof location 7. The exposed portions of the structure are then etchedfour levels to create the structure shown in FIG. 13.

Thereafter, third photoresist mask 58 is removed and an optionalconformal dielectric barrier layer material can be deposited on theexposed surfaces, including over the stair stepped landing pads 60, tocreate a dielectric barrier layer 62. Barrier layer 62 is used as anetching stop and is can be made of silicon nitride. Dielectric filllayer 24 is deposited on the resulting structure. Appropriate vias arethen formed through dielectric fill layer 24 and through the dielectricbarrier layer 62 covering the landing pad 60 of each of terminal layerextensions 40.0-40.7. Electrical conductors 46 are then formed in thevias to provide electrical connection with landing pads 60 of terminallayer extensions 40 and thus with terminal layers 20 capacitors tocreate the structure shown in FIG. 14. Electrical conductors 46 can bemade of the same electrical conductor materials discussed above.However, doped Si, W and Cu may be preferred because of the existingknowledge about chemical mechanical polishing of these electricallyconductive materials. Electrical conductors 46 are identified as46.0-46.7 corresponding to locations 0-7.

More than one interconnect region 44 could be used to access the landingpads 60 at the various levels. Some or all of the landing pads 60 at thedifferent levels could be accessed by the same or different interconnectregion 44.

The process for creating electrical conductors 46 can be referred to asa binary process, based on 2⁰ .. . 2 ^(n-1) withn being the number ofetching steps. That is, first photoresist mask 50 alternatingly covers2⁰ landing pads 60 and exposes 2⁰ landing pads 60; second photoresistmask 54 alternatingly covers 2¹ landing pads 60 and exposes 2¹ landingpads 60; third photoresist mask 58 alternatingly covers 2² landing pads60 and exposes 2² landing pads 60; and so on. Using this binary process,n masks can be used to provide access to 2^(n) landing pads 60 for 2^(n)terminalconductors 46. Thus, using three masks provides access to 8landing pads 60 for 8 terminal conductors 46. Using five masks wouldprovide access to 32 landing pads 60 by 32 electrical conductors 46. Theorder of etching need not be in the order of n−1=0, 1, 2, . . . . Forexample, the first etching step could be with n−1=2, the second could bewith n−1=0, and the third could be with n−1=1.

Further information on similar techniques and methods for connectingelectrical conductors 46 to landing pads 60 are disclosed in U.S. patentapplication Ser. No. 13/049,303, filed 16 Mar. 2011, entitled REDUCEDNUMBER OF MASK FOR IC DEVICE WITH STACKED CONTACT LEVELS; and in U.S.patent application Ser. No. 13/114,931, filed 24 May 2011, entitledMULTILAYER CONNECTION STRUCTURE AND MAKING METHOD, the disclosures ofwhich are incorporated by reference. These two applications and thepresent application have a common assignee.

FIG. 15 is a simplified block diagram of an integrated circuit withstacks of conductive material for both a capacitor and a 3D NAND arrayon a same substrate.

The integrated circuit line 975 includes a 3D NAND flash memory array960, implemented as described herein, on a semiconductor substrate withstacks of conductive material and with capacitors with stacks ofconductive material. A row decoder 961 is coupled to a plurality of wordlines 962, and arranged along rows in the memory array 960. A columndecoder 963 is coupled to a plurality of SSL lines 964 arranged alongcolumns corresponding to stacks in the memory array 960 for reading andprogramming data from the memory cells in the array 960. A plane decoder958 is coupled to a plurality of planes in the memory array 960 via bitlines 959. Addresses are supplied on bus 965 to column decoder 963, rowdecoder 961 and plane decoder 958. Sense amplifiers and data-instructures in block 966 are coupled to the column decoder 963 in thisexample via data bus 967. Data is supplied via the data-in line 971 frominput/output ports on the integrated circuit 975 or from other datasources internal or external to the integrated circuit 975, to thedata-in structures in block 966. In the illustrated embodiment, othercircuitry 974 is included on the integrated circuit, such as a generalpurpose processor or special purpose application circuitry, or acombination of modules providing system-on-a-chip functionalitysupported by the NAND flash memory cell array. Data is supplied via thedata-out line 972 from the sense amplifiers in block 966 to input/outputports on the integrated circuit 975, or to other data destinationsinternal or external to the integrated circuit 975.

A controller implemented in this example using bias arrangement statemachine 969 controls the application of bias arrangement supply voltagegenerated or provided through the voltage supply or supplies in block968, such as read, erase, program, erase verify and program verifyvoltages. The controller can be implemented using special-purpose logiccircuitry as known in the art. In alternative embodiments, thecontroller comprises a general-purpose processor, which may beimplemented on the same integrated circuit, which executes a computerprogram to control the operations of the device. In yet otherembodiments, a combination of special-purpose logic circuitry and ageneral-purpose processor may be utilized for implementation of thecontroller.

The substrate also includes capacitors with stacks of conductivematerial 999 on the same substrate as the 3D NAND flash memory array960.

The above descriptions may have used terms such as above, below, top,bottom, over, under, et cetera. These terms may be used in thedescription and claims to aid understanding of the invention and notused in a limiting sense.

FIG. 16 is a simplified block diagram of a computer system 110 thatimplements software incorporating aspects of the present invention.While the present paper indicates individual steps carrying outspecified operations, it will be appreciated that each step is actuallyimplemented with software instructions that cause the computer system110 to operate in the specified manner. The group of softwareinstructions and data to implement a particular step, in conjunctionwith the processing subsystem and other components of the computersystem which enable such software instructions to be executed,constitute a module which implements the particular step.

Computer system 210 typically includes a processor subsystem 214 whichcommunicates with a number of peripheral devices via bus subsystem 212.These peripheral devices may include a storage subsystem 224, comprisinga memory subsystem 226 and a file storage subsystem 228, user interfaceinput devices 222, user interface output devices 220, and a networkinterface subsystem 216. The input and output devices allow userinteraction with computer system 210. Network interface subsystem 216provides an interface to outside networks, including an interface tocommunication network 218, and is coupled via communication network 218to corresponding interface devices in other computer systems.Communication network 218 may comprise many interconnected computersystems and communication links. These communication links may bewireline links, optical links, wireless links, or any other mechanismsfor communication of information. While in one embodiment, communicationnetwork 218 is the Internet, in other embodiments, communication network218 may be any suitable computer network.

The physical hardware component of network interfaces are sometimesreferred to as network interface cards (NICs), although they need not bein the form of cards: for instance they could be in the form ofintegrated circuits (ICs) and connectors fitted directly onto amotherboard, or in the form of macrocells fabricated on a singleintegrated circuit chip with other components of the computer system.

User interface input devices 222 may include a keyboard, pointingdevices such as a mouse, trackball, touchpad, or graphics tablet, ascanner, a touch screen incorporated into the display, audio inputdevices such as voice recognition systems, microphones, and other typesof input devices. In general, use of the term “input device” is intendedto include all possible types of devices and ways to input informationinto computer system 210 or onto computer network 218.

User interface output devices 220 may include a display subsystem, aprinter, a fax machine, or nonvisual displays such as audio outputdevices. The display subsystem may include a cathode ray tube (CRT), aflat panel device such as a liquid crystal display (LCD), a projectiondevice, or some other mechanism for creating a visible image. Thedisplay subsystem may also provide non visual display such as via audiooutput devices. In general, use of the term “output device” is intendedto include all possible types of devices and ways to output informationfrom computer system 110 to the user or to another machine or computersystem.

Non-transitory storage subsystem 224 stores the basic programming anddata constructs that provide the functionality of certain embodiments ofthe present technology. For example, the various modules implementingthe functionality of certain embodiments of the invention may be storedin storage subsystem 224. Some examples are EDA programs for a cell orlayout including stacks of conductive material for NAND memory arraysand capacitors on the same substrate as described herein. These softwaremodules are generally executed by processor subsystem 214. Storagesubsystem 224 also represents storage accessible to the computer systemon which the various software mentioned herein are stored. In anotherembodiment some or all of the software is located on storage accessibleto the computer system via the network 218.

Memory subsystem 226 typically includes a number of memories including amain random access memory (RAM) 230 for storage of instructions and dataduring program execution and a read only memory (ROM) 232 in which fixedinstructions are stored. File storage subsystem 228 provides persistentstorage for program and data files, and may include a hard disk drive, afloppy disk drive along with associated removable media, a CD ROM drive,an optical drive, or removable media cartridges. The databases andmodules implementing the functionality of certain embodiments of theinvention may have been provided on a computer readable medium such asone or more CD-ROMs, and may be stored by file storage subsystem 228.The host memory 226 contains, among other things, computer instructionswhich, when executed by the processor subsystem 214, cause the computersystem to operate or perform functions as described herein. As usedherein, processes and software that are said to run in or on “the host”or “the computer”, execute on the processor subsystem 214 in response tocomputer instructions and data in the host memory subsystem 226including any other local or remote storage for such instructions anddata.

Bus subsystem 212 provides a mechanism for letting the variouscomponents and subsystems of computer system 210 communicate with eachother as intended. Although bus subsystem 212 is shown schematically asa single bus, alternative embodiments of the bus subsystem may usemultiple busses.

Computer system 210 itself can be of varying types including a personalcomputer, a portable computer, a workstation, a computer terminal, anetwork computer, a television, a mainframe, a server farm, or any otherdata processing system or user device. Due to the ever changing natureof computers and networks, the description of computer system 210 isintended only as a specific example for purposes of illustrating certainembodiments of the present invention. Many other configurations ofcomputer system 210 are possible having more or less components than thecomputer system depicted.

FIG. 16A shows a nontransitory computer readable medium 240 which storesa cell or layout 280 with stacks of conductive material in a NAND arrayand in a capacitor on a same substrate. The nontransitory computerreadable medium can be any of the nontransitory memories discussed inconnection with the storage subsystem 224.

While the present invention is disclosed by reference to the preferredembodiments and examples detailed above, it is to be understood thatthese examples are intended in an illustrative rather than in a limitingsense. It is contemplated that modifications and combinations will occurto those skilled in the art, which modifications and combinations willbe within the spirit of the invention and the scope of the followingclaims. Any and all patents, patent applications and printedpublications referred to above are incorporated by reference.

1. An integrated circuit comprising: a substrate; a 3D NAND memory arraywith a stack of conductive strips; and a capacitor with a stack ofcapacitor terminal strips, wherein multiple conductive strips in thestack of conductive strips and multiple capacitor terminal strips of thestack of capacitor terminal strips share a same plurality of planepositions relative to the substrate, different plane positions in thesame plurality of plane positions characterize different capacitorterminal strips in the stack of capacitor terminal strips and differentconductive strips in the stack of conductive strips, and a same planeposition characterizing both a conductive strip in the stack ofconductive strips and a capacitor terminal strip in the stack ofcapacitor terminal strips indicates that the conductive strip and thecapacitor terminal strip have a same vertical position relative to eachother.
 2. The integrated circuit of claim 1, wherein the stack ofconductive strips is at least one of: transistor channels in the 3D NANDmemory array, conductors routing signals that select memory cells in the3D NAND memory array, and conductors routing output from the 3D NANDmemory array.
 3. The integrated circuit of claim 1, wherein the 3D NANDmemory array is a vertical gate memory array, and the conductive stripsin the stack are NAND transistor channels in the vertical gate memoryarray.
 4. The integrated circuit of claim 1, wherein the 3D NAND memoryarray is a vertical channel memory array, and the conductive strips inthe stack are word lines in the vertical channel memory array.
 5. Theintegrated circuit of claim 1, wherein the stack of capacitor terminalstrips includes a first plurality of capacitor terminal stripsalternating with a second plurality of capacitor terminal strips, thefirst plurality of capacitor terminal strips electrically connectedtogether and the second plurality of capacitor terminal stripselectrically connected together.
 6. The integrated circuit of claim 1,wherein the stack of capacitor terminal strips has a first end and asecond end, multiple capacitor terminal strips in the stack of capacitorterminal strips electrically connected together at the first end,multiple capacitor terminal strips in the stack of capacitor terminalstrips electrically connected together at the second end, furthercomprising: a conductive plug electrically connected to at least one ofthe capacitor terminal strips at an intermediate point in between thefirst end and the second end.
 7. The integrated circuit of claim 1,wherein the stack of capacitor terminal strips is one of a plurality ofstacks of capacitor terminal strips having lengths between first endsand second ends, the plurality of stacks of capacitor terminal stripsincluding the first plurality of capacitor terminal strips alternatingwith the second plurality of capacitor terminal strips, the firstplurality of capacitor terminal strips in the plurality of stacks ofcapacitor terminal strips electrically connected together via the firstends and at intermediate points in between the first ends and secondends. 8-14. (canceled)
 15. A method of making an integrated circuit,comprising: making a 3D NAND memory array with a stack of conductivestrips and a capacitor with a stack of capacitor terminal strips,including: in a same etch, defining the stack of conductive strips andthe stack of capacitor terminal strips, wherein multiple conductivestrips in the stack of conductive strips and multiple capacitor terminalstrips of the stack of capacitor terminal strips share a same pluralityof plane positions relative to the substrate, different plane positionsin the same plurality of plane positions characterize differentcapacitor terminal strips in the stack of capacitor terminal strips anddifferent conductive strips in the stack of conductive strips, and asame plane position characterizing both a conductive strip in the stackof conductive strips and a capacitor terminal strip in the stack ofcapacitor terminal strips indicates that the conductive strip and thecapacitor terminal strip have a same vertical position relative to eachother. a 3D NAND memory array with a stack of conductive strips.
 16. Themethod of claim 15, wherein the stack of conductive strips is at leastone of: transistor channels in the 3D NAND memory array, conductorsrouting signals that select memory cells in the 3D NAND memory array,and conductors routing output from the 3D NAND memory array.
 17. Themethod of claim 15, wherein the 3D NAND memory array is a vertical gatememory array, and the conductive strips in the stack are NAND transistorchannels in the vertical gate memory array.
 18. The method of claim 15,wherein the 3D NAND memory array is a vertical channel memory array, andthe conductive strips in the stack are word lines in the verticalchannel memory array.
 19. The method of claim 15, wherein the stack ofcapacitor terminal strips includes a first plurality of capacitorterminal strips alternating with a second plurality of capacitorterminal strips, the first plurality of capacitor terminal stripselectrically connected together and the second plurality of capacitorterminal strips electrically connected together.
 20. The method of claim15, wherein the stack of capacitor terminal strips has a first end and asecond end, multiple capacitor terminal strips in the stack of capacitorterminal strips electrically connected together at the first end,multiple capacitor terminal strips in the stack of capacitor terminalstrips electrically connected together at the second end, furthercomprising: a conductive plug electrically connected to at least one ofthe capacitor terminal strips at an intermediate point in between thefirst end and the second end.
 21. The method of claim 15, wherein thestack of capacitor terminal strips is one of a plurality of stacks ofcapacitor terminal strips having lengths between first ends and secondends, the plurality of stacks of capacitor terminal strips including thefirst plurality of capacitor terminal strips alternating with the secondplurality of capacitor terminal strips, the first plurality of capacitorterminal strips in the plurality of stacks of capacitor terminal stripselectrically connected together via the first ends and at intermediatepoints in between the first ends and second ends.